SMSC DS LAN91C965v&3v
Page 1
Rev. 09/19/2002
PRELIMINARY
LAN91C96
Non-PCI Single-Chip Full Duplex
Ethernet Controller with Magic
Packet
Datasheet
Product Features
Non-PCI Single-Chip Ethernet Controller
A Subset of Motorola 68000 Bus Interface
Support
Fully Supports Full Duplex Switched Ethernet
Supports Enhanced Transmit Queue
Management
6K Bytes of On-Chip RAM
Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
Automatic Detection of TX/RX Polarity Reversal
Enhanced Power Management Features
Supports "Magic Packet" Power Management
Technology
Simultasking Early Transmit and Early Receive
Functions
Enhanced Early Transmit Function
Receive Counter for Enhanced Early Receive
Hardware Memory Management Unit
Optional Configuration via Serial EEPROM
Interface (Jumperless)
Supports single +5V or +3.3V (for Revisions E
and Later) VCC Designs
Supports Mixed Voltage External PHY Designs
1
Low Power CMOS Design
100 Pin QFP and TQFP (1.0 mm body
Thickness) Packages
Pin Compatible with the LAN91C92 and
LAN91C94
Bus Interface
Direct Interface to Local Bus, PCMCIA, and
68000 Buses with No Wait States
Flexible Bus Interface
16 Bit Data and Control Paths
Fast Access Time
1
Refer to Description of Pin Functions on Page 16 for
5V tolerant pins
Pipelined Data Path
Handles Block Word Transfers for any
Alignment
High Performance Chained ("Back-to-Back")
Transmit and Receive
Pin Compatible with the LAN91C92 (in Local
Bus Mode) and the LAN91C94 in Both Local
Bus and PCMCIA Modes
Dynamic Memory Allocation Between Transmit
and Receive
Flat Memory Structure for Low CPU Overhead
Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
Supports Boot PROM for Diskless Local Bus
Applications
Network Interface
Integrated 10BASE-T Transceiver Functions:
-
Driver and Receiver
-
Link Integrity Test
-
Receive Polarity Detection and Correction
Integrated AUI Interface
10 Mb/s Manchester Encoding/Decoding and
Clock Recovery
Automatic Retransmission, Bad Packet
Rejection, and Transmit Padding
External and Internal Loopback Modes
Four Direct Driven LEDs for Status/ Diagnostics
Software Drivers
LAN9000 Drivers for Major Network Operating
Systems Utilizing Local Bus or PCMCIA
Interface
Software Drivers Compatible with the
LAN91C92, LAN91C94, LAN91C100FD (100
Mb/s), and LAN91C110 (100 Mb/s) Controllers
in Local Bus Mode
Software Drivers Utilize Full Capability of 32 Bit
Microprocessor
N
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Rev. 09/19/2002
Page 2
SMSC DS LAN91C965v&3v
PRELIMINARY
ORDERING INFORMATION
Order Numbers:
LAN91C96 QFP
LAN91C96 TQFP
STANDARD MICROSYSTEMS CORPORATION (SMSC) 2002
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the
trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;
consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is
believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product
descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The
provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or
others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms
of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as
anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC
products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or
contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing
and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement,
may be obtained by visiting SMSC's website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
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OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
SMSC DS LAN91C965v&3v
Page 3
Rev. 09/19/2002
PRELIMINARY
TABLE OF CONTENTS
Chapter 1
General Description _________________________________________________________________________ 6
Chapter 2
Overview __________________________________________________________________________________ 7
Chapter 3
Pin Configurations_________________________________________________________________________ 10
3.1
Local Bus vs. PCMCIA vs. 68000 Pin Requirements ________________________________________________ 14
Chapter 4
Description of Pin Functions ________________________________________________________________ 16
4.1
Buffer Symbols _______________________________________________________________________________ 20
Chapter 5
Functional Description _____________________________________________________________________ 22
5.1
Buffer Memory _______________________________________________________________________________ 23
5.2
Interrupt Structure____________________________________________________________________________ 30
5.3
Reset Logic___________________________________________________________________________________ 31
5.4
Power Down Logic States_______________________________________________________________________ 31
5.5
LAN91C96 Power Down States __________________________________________________________________ 32
5.6
PCMCIA CONFIGURATION REGISTERS DESCRIPTION ________________________________________ 35
Chapter 6
Frame Format in Buffer Memory for Ethernet __________________________________________________ 37
Chapter 7
Registers Map in I/O Space __________________________________________________________________ 41
7.1
I/O Space Access ______________________________________________________________________________ 41
7.2
I/O Space Registers Description _________________________________________________________________ 41
Chapter 8
Theory of Operation________________________________________________________________________ 65
8.1
Typical Flow of Events for Transmit (Auto Release = 0) _____________________________________________ 67
8.2
Typical Flow of Events for Transmit (Auto Release = 1) _____________________________________________ 68
8.3
Flow of Events for Receive ______________________________________________________________________ 69
Chapter 9
Functional Description of the Blocks __________________________________________________________ 79
9.1
Memory Management Unit _____________________________________________________________________ 79
9.2
Arbiter ______________________________________________________________________________________ 79
9.3
Bus Interface _________________________________________________________________________________ 80
9.4
Wait State Policy ______________________________________________________________________________ 80
9.5
Arbitration Considerations _____________________________________________________________________ 81
9.6
DMA Block __________________________________________________________________________________ 81
9.7
Packet Number FIFOS_________________________________________________________________________ 82
9.8
CSMA Block _________________________________________________________________________________ 84
9.9
Network Interface _____________________________________________________________________________ 85
9.10
10Base-T___________________________________________________________________________________ 86
9.11
AUI _______________________________________________________________________________________ 86
9.12
Physical Interface ___________________________________________________________________________ 86
9.13
Transmit Functions__________________________________________________________________________ 86
9.13.1
Manchester Encoding _______________________________________________________________________ 86
9.13.2
Transmit Drivers ___________________________________________________________________________ 87
9.13.3
Jabber Function____________________________________________________________________________ 87
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Rev. 09/19/2002
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SMSC DS LAN91C965v&3v
PRELIMINARY
9.13.4
SQE Function _____________________________________________________________________________ 87
9.14
Receive Functions ___________________________________________________________________________ 87
9.14.1
Receive Drivers____________________________________________________________________________ 87
9.14.2
Manchester Decoder and Clock Recovery _______________________________________________________ 87
9.14.3
Squelch Function __________________________________________________________________________ 87
9.14.4
Reverse Polarity Function____________________________________________________________________ 88
9.14.5
Collision Detection Function _________________________________________________________________ 88
9.14.6
Link Integrity _____________________________________________________________________________ 88
Chapter 10
Board Setup Information____________________________________________________________________ 89
10.1
Diagnostic LEDs ____________________________________________________________________________ 90
10.2
Bus Clock Considerations ____________________________________________________________________ 90
10.3
68000 Bus Interface__________________________________________________________________________ 90
Chapter 11
Operational Description_____________________________________________________________________ 92
11.1
Maximum Guaranteed Ratings* _______________________________________________________________ 92
11.2
DC Electrical Characteristics _________________________________________________________________ 92
Chapter 12
Timing Diagrams __________________________________________________________________________ 99
Chapter 13
LAN91C96 Revisions ______________________________________________________________________ 125
LIST OF FIGURES
Figure 3.1 - LAN91C96 100 Pin QFP...........................................................................................................................10
Figure 3.2 - LAN91C96 100 Pin TQFP.........................................................................................................................11
Figure 3.3 - LAN91C96 System Block Diagram ...........................................................................................................12
Figure 3.4 System Diagram for Local Bus with Boot Prom .......................................................................................13
Figure 4.1 - LAN91C96 Internal Block Diagram ...........................................................................................................21
Figure 5.1 Mapping and Paging vs. Receive and Transmit Area ..............................................................................24
Figure 5.2 Transmit Queues and Mapping................................................................................................................25
Figure 5.3 Receive Queues and Mapping.................................................................................................................26
Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path...................................................................................27
Figure 5.5 Logical Address Generation and Relevant Registers...............................................................................28
Figure 6.1 Data Frame Format..................................................................................................................................37
Figure 6.2 - LAN91C96 Registers ................................................................................................................................40
FIGURE 7.1 - INTERRUPT STRUCTURE....................................................................................................................61
Figure 8.1 Interrupt Service Routine .........................................................................................................................70
Figure 8.2 - RX INTR ...................................................................................................................................................71
Figure 8.3 -TX INTR.....................................................................................................................................................72
Figure 8.4 -TXEMPTY INTR ........................................................................................................................................73
Figure 8.5 - DRIVER SEND AND ALLOCATE ROUTINES..........................................................................................74
FIGURE 8.6 - INTERRUPT GENERATION FOR TRANSMIT; RECEIVE, MMU .........................................................78
FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS.........................................................84
FIGURE 10.1 - 64 X 16 SERIAL EEPROM MAP .........................................................................................................91
Figure 12.1 Card Configuration Registers Read/Write PCMCIA Mode (A15=1) ....................................................99
Figure 12.2 Local Bus Consecutive Read Cycles ...................................................................................................100
Figure 12.3 - PCMCIA Consecutive Read Cycles ......................................................................................................101
Figure 12.4 Local Bus Consecutive Write Cycles....................................................................................................102
Figure 12.5 - PCMCIA Consecutive Write Cycles ......................................................................................................103
Figure 12.6 Local Bus Consecutive Read and Write Cycles ...................................................................................104
Figure 12.7 Data Register Special Read Access ....................................................................................................105
Figure 12.8 Data Register Special Write Access.....................................................................................................106
Figure 12.9 - 8-Bit Mode Register Cycles ..................................................................................................................107
Figure 12.10 - 68000 Read Timing.............................................................................................................................108
Figure 12.11 - 68000 Write Timing.............................................................................................................................109
Figure 12.12 External ROM Read Access ..............................................................................................................110
Figure 12.13 Local Bus Register Access When Using Bale....................................................................................111
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
SMSC DS LAN91C965v&3v
Page 5
Rev. 09/19/2002
PRELIMINARY
Figure 12.14 External ROM Read Access Using Bale ............................................................................................112
Figure 12.15 - EEPROM Read...................................................................................................................................113
Figure 12.16 - EEPROM Write ...................................................................................................................................114
Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) .................................................................................115
Figure 12.18 External ENDEC Interface Start of Transmit ...................................................................................115
Figure 12.19 External ENDEC Interface Receive Data ........................................................................................116
Figure 12.20 Differential Output Signal Timing (10BASE-T and AUI) .....................................................................117
Figure 12.21 Receive Timing Start of Frame (AUI and 10BASE-T) .....................................................................118
Figure 12.22 Receive Timing End of Frame (AUI and 10BASE-T).......................................................................119
Figure 12.23 Transmit Timing End of Frame (AUI and 10BASE-T)......................................................................120
Figure 12.24 Collision Timing (AUI) ........................................................................................................................121
Figure 12.25 Memory Read Timing.........................................................................................................................121
Figure 12.26 Input Clock Timing .............................................................................................................................122
Figure 12.27 Memory Write Timing .........................................................................................................................122
Figure 12.28 - 100 PIN QFP Package........................................................................................................................123
Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124
LIST OF TABLES
Table 5.1 - LAN91C96 Address Space ........................................................................................................................29
Table 5.2 - Bus Transactions In LOCAL BUS Mode ....................................................................................................29
Table 5.3 - Bus Transactions In PCMCIA Mode...........................................................................................................30
Table 5.4 - Bus Transactions In 68000 Mode................................................................................................................30
Table 5.5 - Interrupt Merging........................................................................................................................................31
Table 5.6 - LOCAL BUS Mode Defined States (Refer To Table 5.7 For Next States To Wake-Up Events).................32
Table 5.7- LOCAL BUS Mode......................................................................................................................................32
Table 5.8 - PCMCIA Mode (Refer To Table 5.7 For Next States To Wake-Up Events) ...............................................33
Table 5.9 - PCMCIA Mode ...........................................................................................................................................33
Table 7.1 - Transmit Loop ............................................................................................................................................44
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